Continuous Integration
Continuous Deployment

I’m Zidane Karim, an undergraduate engineering student interested in software, infrastructure, and machine learning. Currently learning how to build systems that are useful to the everyday student.

Selected projects

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02

Cache-Money 32-bit MIPS CPU

A pipelined 32-bit core in SystemVerilog paired with a custom two-pass Python assembler.

SystemVerilog / Python / Computer Architecture / Verification[writeup]

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