Project / 2026-04-20
Cache-Money 32-bit MIPS CPU
A pipelined 32-bit core in SystemVerilog paired with a custom two-pass Python assembler.
A complete 32-bit MIPS-compatible processor synthesized in SystemVerilog. Features custom datapath routing, discrete ALU execution units, and control logic supporting R-, I-, and J-type instruction sets. Paired with a custom Python assembler supporting symbol tables, exception trapping, and automated testbench regression suites.